1. Field
Aspect of the innovations herein relate generally to memory and/or memory latching and, more specifically, to systems and methods of memory and memory operation, such as fast address access for read and write in the same cycle.
2. Description of Related Information
In many memory circuits, inputs are registered by a clock in the SRAM. Thus for proper operation, all read or write operations should occur after the rising edge of a clock. For synchronous operation, then, there must be a setup time and hold time to ensure that an input is properly registered. FIG. 1A is a block diagram of an existing memory circuit 100. External input 110 and clock 120 signals are fed into an input register 130. Here, the usage of setup time is only pertinent to the input register. The output of the input register 130 can be fed into a pre-decoder 140 which in turn supplies a signal to a decoder 150, which in turn supplies a signal to a memory array 160. FIG. 1B is a block diagram of another prior art memory circuit 100. In this embodiment, an external input 110 is first supplied to a pre-decoder 140. The output of the pre-decoder 140 and a clock 120 are supplied to an input register 130 which in turn supplies a signal to a decoder 150, which in turn supplies a signal to a memory array 160. In both cases, an input register 130 is used to ensure synchronous memory circuit operation.
However, there is a need for systems and methods that provide for fast address access for read and write in the same cycle and/or other advantages over such existing circuitry.